HD6432621 Hitachi, HD6432621 Datasheet - Page 740

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

21A.4 Sleep Mode
21A.4.1 Sleep Mode
When the SLEEP instruction is executed when the SBYCR SSBY bit = 0, the CPU enters the
sleep mode. In sleep mode, CPU operation stops but the contents of the CPUís internal registers
are retained. Other supporting modules do not stop.
21A.4.2 Exiting Sleep Mode
Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.
Exiting Sleep Mode by Interrupts: When an interrupt occurs, sleep mode is exited and interrupt
exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other
than NMI are masked by the CPU.
Exiting Sleep Mode by RES pin: Setting the RES pin level Low selects the reset state. After the
stipulated reset input duration, driving the RES pin High starts the CPU performing reset
exception processing.
Exiting Sleep Mode by STBY Pin: When the STBY pin level is driven Low, a transition is made
to hardware standby mode.
21A.5 Module Stop Mode
21A.5.1 Module Stop Mode
Module stop mode can be set for individual on-chip supporting modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
Table 21A-3 shows MSTP bits and the corresponding on-chip supporting modules.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the SCI, A/D converter and HCAN are retained.
After reset clearance, all modules other than DTC are in module stop mode.
When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
696