HD6432621 Hitachi, HD6432621 Datasheet - Page 656

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
18.1.2
The on-chip RAM is controlled by SYSCR. Table 18-1 shows the address and initial value of
SYSCR.
Table 18-1 RAM Register
Name
System control register
Note: * Lower 16 bits of the address.
18.2
18.2.1
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Note: When the DTC is used, the RAME bit must be set to 1.
Bit 0
RAME
0
1
612
Bit
Initial value
R/W
Register Configuration
Register Descriptions
System Control Register (SYSCR)
Description
On-chip RAM is disabled
On-chip RAM is enabled
:
:
:
MACS
R/W
7
0
6
0
Abbreviation
SYSCR
INTM1
R/W
5
0
INTM0
R/W
4
0
R/W
R/W
NMIEG
R/W
3
0
Initial Value
H'01
R/W
2
0
1
0
(Initial value)
Address*
H'FDE5
RAME
R/W
0
1

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