HD6432621 Hitachi, HD6432621 Datasheet - Page 231
HD6432621
Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432621.pdf
(1069 pages)
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For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and
writing. If all interrupts are masked, multiple activation sources can be set at one time by writing
data after executing a dummy read on the relevant register.
8.2.8
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by
software.
Bit 7
SWDTE
0
1
Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits
specify a vector number for DTC software activation.
The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit left-
shift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.
Bit
Initial value
R/W
Notes: *1 Only 1 can be written to the SWDTE bit.
DTC Vector Register (DTVECR)
*2 Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.
Description
DTC software activation is disabled
[Clearing conditions]
DTC software activation is enabled
[Holding conditions]
:
:
:
When the DISEL bit is 0 and the specified number of transfers have not ended
When 0 s written to the DISEL bit after a software-activated data transfer end
interrupt (SWDTEND) request has been sent to the CPU
When the DISEL bit is 1 and data transfer has ended
When the specified number of transfers have ended
During data transfer due to software activation
SWDTE
R/(W)*
7
0
1
DTVEC6
R/(W)*
6
0
2
DTVEC5
R/(W)*
5
0
2
DTVEC4
R/(W)*
4
0
2
DTVEC3
R/(W)*
3
0
2
DTVEC2
R/(W)*
2
0
2
DTVEC1
R/(W)*
1
0
2
(Initial value)
DTVEC0
R/(W)*
0
0
2
187
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