HD6432621 Hitachi, HD6432621 Datasheet - Page 612

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

15.3.4
Message reception is performed using mailboxes 0 and 1 to 15. The reception procedure is
described below, and a reception flowchart is shown in figure 15-9.
Initialization (after hardware reset only)
Interrupt and receive message settings
Message reception and interrupts
Initialization (After Hardware Reset Only): These settings should be made while the HCAN is
in bit configuration mode.
568
a. Clearing of IRR0 bit in interrupt register (IRR)
b. Bit rate settings
c. Mailbox transmit/receive settings
d. Mailbox (RAM) initialization
a. CPU interrupt source setting
b. Arbitration field setting
c. Local acceptance filter mask (LAFM) settings
a. Message reception CRC check
b. Data frame reception
c. Remote frame reception
d. Unread message reception
IRR0 clearing
The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby
mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0
should be cleared.
Bit rate settings
Set values relating to the CAN bus communication speed and resynchronization. Refer to Bit
Rate and Bit Timing Setting in 15.3.2, Initialization after Hardware Reset, for details.
Mailbox transmit/receive settings
Each channel has one receive-only mailbox (mailbox 0) plus 15 mailboxes that can be set for
reception. Thus a total of 16 mailboxes can be used for reception. To set a mailbox for
reception, set the corresponding bit to 1 in the mailbox configuration register (MBCR). The
initial setting for mailboxes is 0, designating transmission use. Refer to Mailbox
transmit/receive settings in 15.3.2, Initialization after Hardware Reset, for details.
Receive Mode