HD6432621 Hitachi, HD6432621 Datasheet - Page 110
HD6432621
Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432621.pdf
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2.8.4
In this state the CPU executes program instructions in sequence.
2.8.5
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts operations.
Bus masters other than the CPU are data transfer controller (DTC).
For further details, refer to section 7, Bus Controller.
2.8.6
The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,
software standby mode, hardware standby mode, subsleep mode*, and watch mode*. There are
also three other power-down modes: medium-speed mode, module stop mode, and subactive
mode*. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock.
Module stop mode permits halting of the operation of individual modules, other than the CPU.
Subactive mode*, subsleep mode*, and watch mode* are power-down states using subclock input.
For details, refer to section 21B, Power-Down Modes [H8S/2626 Series].
Note: * Supported only in the H8S/2626 Series; not available in the H8S/2623 Series.
66
Program Execution State
Bus-Released State
Power-Down State
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