PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 92

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

4.1.4
The QuadFALC supports the S
follows:
• The access via registers RSW / XSW
• the access via registers RSA8-4 / XSA4-8
• the access via the 64 byte deep receive/transmit FIFO of the integrated signaling
4.2
The QuadFALC is programmable via a microprocessor interface which enables byte or
word access to all control and status registers.
After RESET the QuadFALC must be first initialized. General guidelines for initialization
are described in section Initialization.
The status registers are read-only and are continuously updated. Normally, the
processor periodically reads the status registers to analyze the alarm status and
signaling data.
Reset
The QuadFALC is forced to the reset state if a high signal is input at port RES for a
minimum period of 10 s. During RESET the QuadFALC needs an active clock on pin
MCLK. All output stages are in a high impedance state, all internal flip-flops are reset and
most of the control registers are initialized with default values.
Semiconductor Group
capable of storing the information for a complete multiframe
controller. This S
stream as well as HDLC frames where the signaling controller automatically
processes
resetting of registers TTR1-4, RTR1-4 and FMR1.ENSA.
The data written to the XFIFO will subsequently transmit in the S
by register XC0.SA8E-4E and the corresponding bits of TSWM.TSA8-4. Any
combination of S
an “all ones” or Flags (CCR1.ITF) will be transmitted. The continuous transmission of
a transparent bit stream, which is stored in the XFIFO, can be enabled.
With the setting of bit MODE.HRAC the received S
receive FIFO.
The access to and from the FIFOs is supported by ISR0.RME/RPF and
ISR1.XPR/ALS.
S
Operational Phase
a
bit Access
the HDLC protocol. Enabling is done by setting of bit CCR1.EITS and
a
a
bit access gives the opportunity to transmit/receive a transparent bit
bits can be selected. After the data have been completely sent out
a
bit signaling of time-slot 0 of every other frame as
92
a
bits can be forwarded to the
Operational Description E1
a
bit positions defined
PEB 22554
09.98