PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 296

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

SIM…
Framer Mode Register 1 (Read/Write)
Value after RESET: 00
FMR1
CTM…
EDL…
PMOD…
Semiconductor Group
7
CTM
FMR0.FRS forces the receiver to lock onto the next available framing
position.
Alarm Simulation
Setting/resetting this bit initiates internal error simulation of: AIS (blue
alarm), loss of signal (red alarm), loss of frame alignment, remote
(yellow) alarm, slip, framing errors, CRC errors, code violations. The
error counters FEC, CVC, CEC, EBC will be incremented.
The selection of simulated alarms is done via the error simulation
counter: FRS2.ESC2-0 which will be incremented with each setting of
bit FMR0.SIM. For complete checking of the alarm indications eight
simulation steps are necessary (FRS2.ESC2-0 = 0 after a complete
simulation).
Channel Translation Mode
0…
1…
Enable DL-Bit Access via Register XDL1-3
Only applicable in F4, F24 or F72 frame format.
0…
1…
PCM Mode
For T1 application this bit must be set high. Switching into T1 mode
the device needs up to 10 sec to settle up to the internal clocking.
FMR1.PMOD of all 4 channels has to be set equally.
H
DL-bit register access. The DL-bit information will be taken from
Channel translation mode 0
Channel translation mode 1
Normal operation. The DL-bits will be taken from system
highway or if enabled via CCR1.EDLX from the XFIFO of the
signaling controller.
the registers XDL1-3 and will overwrite the DL-bits received at
the system highway (pin XDI) or the internal XFIFO of the
signaling controller. However, transmitting contents of registers
XDL1-3 will be disabled if transparent mode is enabled
(FMR4.TM).
EDL
PMOD
296
CRC
Operational Description T1 / J1
ECM
SSD0
0
XAIS
PEB 22554
(x1D)
09.98