PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 359

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

XMB…
XLSC…
XPR…
Interrupt Status Register 2 (Read)
ISR2
All bits are reset when ISR2 is read.
If bit GCR.VIS is set to ‘1’, interrupt statuses in ISR2 may be flagged although they are
masked via register IMR2. However, these masked interrupt statuses neither generate a
signal on INT, nor are visible in register GIS.
FAR…
LFA…
Semiconductor Group
7
FAR
Note: Transmitter and XFIFO are reset and deactivated if this
Transmit Multiframe Begin
This bit is set with the beginning of a transmitted multiframe related to
the internal transmit line interface timing.
Transmit Line Status Change
XLSC is set to one with the rising edge of the bit FRS1.XLO or with
any change of bit FRS1.XLS.
The actual status of the transmit line monitor can be read from the
FRS1.XLS and FRS1.XLO.
Transmit Pool Ready
A data block of up to 32 bytes can be written to the transmit FIFO.
XPR enables the fastest access to XFIFO. It has to be used for
transmission of long frames, back-to-back frames or frames with
shared flags.
Frame Alignment Recovery
The framer has reached synchronization. Set with the falling edge of
bit FSR0.LFA.
It is set also after alarm simulation is finished and the receiver is still
synchron.
Loss of Frame Alignment
The framer has lost synchronization and bit FRS0.LFA is set.
It will be set during alarm simulation.
LFA
condition occurs. They are re-activated not before this
interrupt status register has been read. Thus, XDU should not
be masked via register IMR1.
MFAR
LMFA
359
AIS
Operational Description T1 / J1
LOS
RAR
0
RA
PEB 22554
(x6A)
09.98