PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 63

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

3.7
General
Bit: FMR1.PMOD = 0
PCM line bit rate
Single frame length :
Framing frequency :
HDLC controller
Organization
The operating mode of the QuadFALC is selected by programming the carrier data rate
and characteristics, line code, multiframe structure, and signaling scheme.
The QuadFALC implements all of the standard framing structures for E1 or PCM 30
(CEPT, 2.048 MBit/s) carriers. The internal HDLC- or CAS Controller supports all
signaling procedures including signaling frame synchronization / synthesis and signaling
alarm detection in all framing formats. The time-slot assignment from the PCM line to the
system highway and vv. is performed without any changes of numbering (TS0
TS0, … , TS31
Summary of E1- Framing Modes
• Doubleframe format according to ITU-T G. 704
• Multiframe format according to ITU-T G. 704
• Multiframe format with CRC4 to non CRC4 interworking according to ITU-T G. 706
• Multiframe format with modified CRC4 to non CRC4 interworking
• Multiframe format with CRC4 performance monitoring
After RESET, the QuadFALC is switched into doubleframe format automatically.
Switching between the framing formats is done via bit FMR2.RFS1/0 and FMR3.EXTIW
for the receiver and FMR1.XFS for the transmitter.
Semiconductor Group
CRC4 processing according to ITU-T G. 706
Framer Operating Modes E1
TS31).
:
:
:
256 bit, No. 1 … 256
8 kHz
nx64 kbit/s , n = 1 ... 32 or nx4 kbit/s , n=1 ... 5
32 time-slots, No. 0 … 31
with 8 bits each, No. 1 … 8
2.048 MBit/s
63
Functional Description E1
PEB 22554
09.98