PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 260

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

• Error counter
• Status : errored second
• Second timer
Clear Channel Capability
For support of common T1 applications, clear channels can be specified via the 3-byte
register bank CCB1 … CCB3. In this mode the contents of selected transmit time-slots
Semiconductor Group
The QuadFALC offers six error counters each of them has a length of 16 bit. They
record code violations, framing bit errors, CRC6 bit errors, errored blocks and the
number of received multiframes in the asynchronous state or the changes of frame
alignment (COFA). Counting of the multiframes in the asyn. state and the COFA
parameter is done in a 6 / 2 bit counter. Each of the error counter is buffered. Updating
the buffer is done in two modes:
- one second accumulation
- on demand via handshake with writing to the DEC register
In the one second mode an internal/external one second timer will update these
buffers and reset the counter to accumulate the error events in the next one second
period. The error counter can not overflow. Error events occuring during reset will not
lost.
The QuadFALC supports the error performance monitoring by detecting the following
alarms or error events in the received data:
framing errors , CRC errors , code violations , loss of frame alignment , loss of signal,
alarm indication signal , receive and transmit slips.
With a programmable interrupt mask register ESM all these alarms or error events
could generate an Errored Second interrupt (ISR3.ES) if enabled.
Additionally per channel a one second timer interrupt could be internally generated to
indicate that the enabled alarm status bits or the error counters have to be checked.
Enabled by GPC1.FSS2-0 the one second timer of the selected channel may be
output on port SEC/FSC (GPC1.CSFP1/0). Optionally if all four channels of the
QuadFALC should synchronized to an external second timer an appropriate clock has
to be provided to pin SEC/FSC. Selecting the external second timer is done with
GCR.SES. Refer also to register GPC1.
clock. In case of Loss of Signal LOS the DCO-R switches automatically to Master
mode. If bit CMR1.DCS is set automatic switching from RCLK to SYNC can be
disabled.
- Automatic freeze signaling:
Updating of the received signaling information is controlled by the freeze signaling
status. The freeze signaling status is automatically activated if a Loss of Signal, or
a Loss of Multiframe Alignment or a receive slip occures. The internal signaling
buffer RS1-12 is froozen. Optionally automatic freeze signaling may be disabled by
setting bit SIC3.DAF.
260
Functional Description T1 / J1
PEB 22554
09.98