PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 85

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

4
4.1
The HDLC controller can be programmed to operate in various modes, which are
different in the treatment of the HDLC frame in receive direction. Thus, the receive data
flow and the address recognition features can be performed in a very flexible way, to
satisfy almost any practical requirements.
There are 4 different operating modes which can be set via the MODE register.
4.1.1
All frames with valid addresses are forwarded directly via the RFIFO to the system
memory.
Depending on the selected address mode, the QuadFALC can perform a 1 or 2 byte
address recognition (MODE.MDS0).
If a 2-byte address field is selected, the high address byte is compared with the fixed
value FEH or FCH (group address) as well as with two individually programmable values
in RAH1 and RAH2 registers. According to the ISDN LAPD protocol, bit 1 of the high byte
address will be interpreted as COMMAND/RESPONSE bit (C/R) and will be excluded
from the address comparison.
Similarly, two compare values can be programmed in special registers (RAL1, RAL2) for
the low address byte. A valid address will be recognized in case the high and low byte of
the address field correspond to one of the compare values. Thus, the QuadFALC can be
called (addressed) with 6 different address combinations. HDLC frames with address
fields that do not match any of the address combinations, are ignored by the FALC.
In case of a 1-byte address, RAL1 and RAL2 will be used as compare registers. The
HDLC control field, data in the I-field and an additional status byte are temporarily stored
in the RFIFO. Additional information can also be read from a special register (RSIS).
As defined by the HDLC protocol, the QuadFALC perform the zero bit insertion/deletion
(bit-stuffing) in the transmit/receive data stream automatically. That means, it is
guaranteed that at least after 5 consecutive “1”-s a “0” will appear.
Non-Auto-Mode (MODE.MDS2-1=01)
Characteristics: address recognition, FLAG - and CRC generation/check, bit-stuffing
All frames with valid addresses are forwarded directly via the RFIFO to the system
memory.
Transparent Mode 1 (MODE.MDS2-0=101)
Characteristics: address recognition, FLAG - and CRC generation/check, bit-stuffing
Semiconductor Group
Operational Description E1
Signaling Controller Operating Modes
HDLC Mode
85
Operational Description E1
PEB 22554
09.98