PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 307

no-image

PEB22554

Manufacturer Part Number
PEB22554
Description
ICs for Communications
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEB22554H/T
Manufacturer:
INF
Quantity:
5 510
Part Number:
PEB22554H/T
Manufacturer:
OMRON
Quantity:
5 510
Part Number:
PEB22554HT
Manufacturer:
INFINEON
Quantity:
325
Part Number:
PEB22554HT V1.3
Quantity:
1 078
Part Number:
PEB22554HT V1.3
Manufacturer:
Infineon
Quantity:
490
Part Number:
PEB22554HT2.1
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Part Number:
PEB22554HTV1.3
Manufacturer:
INFIEON
Quantity:
20 000
Part Number:
PEB22554HTV2.1
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Part Number:
PEB22554V1.3
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
RCO10…RCO8…Receive Offset / Receive Frame Marker Offset
Receive Control 1 (Read/Write)
Value after RESET: 9C
RC1
RTO7…RTO0… Receive Offset / Receive Frame Marker Offset
Semiconductor Group
7
RTO7
0
5
Depending on the RP(A-D) pin function different offsets could be
programmed. The SYPR and the RFM pin function could not be
selected in parallel.
Receive Offset (PC(1-4).RPC(2-0) = 000)
Initial value loaded into the receive bit counter at the trigger edge of
SCLKR when the synchronous pulse at port SYPR is active (see
figure 51).
Calculation of delay time T (SCLKR cycles) depends on the value X
of the „Receive Offset“ register RC1/0. Refer to register RC1.
Depending on the RP(A-D) pin function different offsets could be
programmed. The SYPR and the RFM pin function could not be
selected in parallel.
Receive Offset (PC(1-4).RPC(2-0) = 000)
Initial value loaded into the receive bit counter at the trigger edge of
SCLKR when the synchronous pulse at port SYPR is active (see
figure 51).
Calculation of delay time T (SCLKR cycles) depends on the value X
of the „Receive Offset“ register RC1/0:
system clocking rate: modulo 2.048 MHz (SIC2.SSC2 = 0)
0
5
with max. delay = (256*SC/SD) -1
with SC = System clock defined by SIC1.SSC1/0 + SIC2.SSC2
with SD = 2.048 MHz
or
system clocking rate: modulo 1.544 MHz (SIC2.SSC2 = 1)
with max. delay = 193*SC/SD - 1
with SC = System clock defined by SIC1.SSC1/0 + SIC2.SSC2
with SD = 1.544 MHz
T
T
T
T
H
max. delay : X = (200 * SC/SD) + 4 - T
4:
4 :
max. delay : X= 2052 - T
X= 4- T
X = 4- T + (7* SC/SD)
307
Operational Description T1 / J1
0
RTO0
PEB 22554
(x25)
09.98

Related parts for PEB22554