PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 219

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Transmit jitter attenuator
The transmit jitter attenuator DCO-X circuitry generates a „jitterfree“ transmit clock for
each channel and meets the following requirements: PUB 62411, PUB 43802,
TR-TSY 009,TR-TSY 253, TR-TSY 499 and Rec. I.431 and G.703. The DCO-X circuitry
works internally with the same high frequency clock as the receive jitter attenuator it
does. It synchronizes either to the working clock of the transmit backplane interface or
the clock provided by pin TCLK or the receive clock RCLK (remote loop / loop-timed).
The DCO-X attenuates the incoming jitter starting at 6 Hz with 20 dB per decade fall off.
With the jitter attenuated clock, which is directly dependent on the phase difference of
the incoming clock and the jitter attenuated clock, data is read from the transmit elastic
buffer (2 frames) or from the JATT buffer (2 frames, remote loop) Wander with a jitter
frequency below 6 Hz are passed transparentely.
The DCO-X accepts gapped clocks which are used in ATM or SDH/SONET applications.
The jitter attenuated clock is output on pin XCLK.
The transmit jitter attenuator could be disabled. In that case data is read from the
transmit elastic buffer with the clock sourced by pin TCLK (1.544 or 6.176 MHz).
Synchronization between SCLKX and TCLK has to done externally.
In the loop-timed clock configuration (LIM2.ELT) the DCO-X circuitry generates a
transmit clock which is frequency synchronized to RCLK. In this configuration the
transmit elastic buffer has to be enabled.
Figure 47
Clocking in Remote Loop Configuration
Semiconductor Group
RL1/2
RDIP/N
ROID
XL1/2
XDOP/N
XOID
DRS
Equalizer
Driver
Line
Shaper
DPLL
Pulse
219
DRS
RCLK
RCLK
Attenuator
Transmit
Buffer
JATT
Jitter
Functional Description T1 / J1
RCLK
Decoder
Encoder
Clock
Line
Line
Unit
PEB 22554
Receive
Data
Transmit
Data
MCLK
ITS10299
09.98