PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 136

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

System Interface Control 2 (Read/Write)
Value after RESET: 00
SIC2
FFS …
SSF …
CRB …
SICS2 …0
Semiconductor Group
7
FFS
Serial Signaling Format
Center Receive Elastic Buffer
System Interface Channel Select
Force Freeze Signaling
Setting this bit disables updating of the receive signaling buffer and
current signaling information is frozen. After resetting this bit and
receiving a complete superframe updating of the signaling buffer is
started again. The freeze signaling status could be also automatically
generated by detecting the Loss of Signal alarm or a Loss of CAS
Frame Alignment or a receive slip (only if external register access via
RSIG is enabled). This automatic freeze signaling function is logically
ored with this bit.
The current internal freeze signaling status is output on pin RP(A-D)
/ pin function FREEZ which is selected by PC(1-4).RPC(2-0) = 110.
Additionally this status is also available in register SIS.SFS.
Only applicable if pin function R/XSIG is selected.
0…
1…
Only applicable if the time-slot assigner is disabled ( PC1-4.RPC2-0
= 001 ) , no external or internal synchronous pulse receive is
generated.
A transition from low to high will force a receive slip and the read-
pointer of the receive elastic buffer is centered. The delay through the
buffer is set to one half of the current buffer size. It should be hold high
for at least two 2.048 MHz periods before it is cleared.
Only applicable if the system clock rate is greater than 2.048 MHz .
Received data is transmitted on pin RDO / RSIG or received on XDI
/ XSIG with the selected system data rate. If the data rate is greater
than 2.048 MBit/s the data is output or sampled in half , a quarter or
a 1/8 of the 125 µsec. They will not be repeated. The time where the
data is active during a 488 nsec time-slot is called in the following a
channel phase. RDO / RSIG are cleared while XDI / XSIG are
SSF
H
Bits 1-4 in all time-slots except time-slots 0 +16 are cleared.
Bits 1-4 in all time-slots except time-slots 0 +16 are set high.
CRB
136
SICS2
SICS1
Operational Description E1
SICS0
0
PEB 22554
(x3F)
09.98