PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 19

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Pin Definitions and Function (cont’d)
Pin No.
133
134
48
69
119, 130,
47, 61
Semiconductor Group
Symbol
MCLK
NC
FSC
SEC
RCLK(1-4)
SYNC
SEC
Input (I)
Output (O)
I
I + PU
I + PU
O
O
I/O + PU
Function
Reference Clock 2.048 MHz
A reference clock of 2.048 MHz +/- 50 ppm
must be provided to this pin.
Not connected
Clock Synchronization
If a clock is detected at the SYNC pin the
DCO-Rs of the QuadFALC synchronize to this
2.048 MHz clock. This pin has an integrated pull
up resistor.
Second Timer Input
A pulse with logical one for at least two
2.048MHz cycles will trigger the internal second
timer.
Enabled with GPC1.FSS2-0 an 8-kHz Frame
Synchronization Pulse is output via this pin.
The synchronization pulse is active high / low
for one 2 MHz cycle (pulse width = 488 ns).
Second Timer Output
Activated high every second for two 2.048 MHz
clock cycles. Enabled with GPC1.CSFP1-0.
Receive Clock
After Reset this port is configured to an input.
Setting of bit PC5.CRP will switch this port to an
output. Input function not defined.
Output function:
CMR1.RS1/0 = 00: Receive Clock extracted
from the incoming data pulses. Frequency:
2048 kHz
CMR1.RS1/0 = 01: RCLK is set high in case of
loss of signal (FRS0.LOS=1).
Optional one of the dejittered system clocks
sourced by DCO-R is clocked out. Clock
frequency: 2048 or 8192 kHz . Selected by
CMR1.RS1/0.
Wih GPC1.R1S1/0 one of the four RCLK(1-4) is
output on RCLK1.
19
Pin Descriptions E1
PEB 22554
09.98