PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 108

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

XCRC…
Receive Timeslot Register 1-4 (Read/Write)
Value after RESET: 00
RTR1
RTR2
RTR3
RTR4
TS0…TS31…
Semiconductor Group
7
TS16
TS24
TS0
TS8
mode is selected, the limits for “Valid Frame” check are modified
(refer to RSIS.VFR).
Transmit CRC ON/OFF
If this bit is set to ‘1’, the CRC checksum will not be generated
internally. It has to be written as the last two bytes in the transmit FIFO
(XFIFO). The transmitted frame will be closed automatically with a
closing flag.
Note: The QuadFALC does not check whether the length of the
Timeslot Register
These bits define the received time-slots on the system highway port
RDO to be extracted to RFIFO and marked. Additionally these
registers will control the RSIGM marker which can be forced high
during the respective time-slots independenltly of bit CCR1.EITS.
A one in the RTR1-4 bits will sample the corresponding time-slots and
send their data to the RFIFO of the signaling controller if bit
CCR1.EITS is set.
Assignments:
TS0
.
.
.
TS31
0
RFIFO.
TS17
TS25
TS1
TS9
The corresponding time-slot is not extracted and stored into the
H
, 00
frame, i.e. the number of bytes to be transmitted makes sense
or not.
time-slot 31
time-slot 0
H
TS10
TS18
TS26
TS2
, 00
H
, 00
TS11
TS19
TS27
TS3
H
108
TS12
TS20
TS28
TS4
TS13
TS21
TS29
TS5
Operational Description E1
TS14
TS22
TS30
TS6
0
TS15
TS23
TS31
TS7
PEB 22554
(x0C)
(x0D)
(x0E)
(x0F)
09.98