PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 39

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

• Recovery:
Receive Jitter Attenuator
The receive jitter attenuator is placed for each channel in the receive path. The working
clock is an internally generated high frequency clock based on the clock provided on pin
MCLK (2.048 MHz). The jitter attenuator meets the requirements of ITU-T I.431, G.
736-739, G.823 and ETSI TBR12/13.
The internal PLL circuitry DCO-R generates an „jitterfree“ output clock which is directly
dependent on the phase difference of the incoming clock and the jitter attenuated
clock.The receive jitter attenuator could be either synchronized to the extracted receive
clock RCLK or to a 2.048 MHz clock provided on pin SYNC. The received data is written
into the receive elastic buffer with RCLK and are read out with the dejittered clock
sourced by DCO-R. The jitter attenuated clock could be output via pins RCLK or SCLKR.
Optionally a 8 kHz clock is provided on pin SEC/FSC.
The DCO-R circuitry attenuates the incoming jittered clock starting at 2 Hz jitter
frequency with 20 dB per decade fall off. Wander with a jitter frequency below 2 Hz will
be passed unattenuated. The intrinsic jitter in the absence of any input jitter is < 0.02 UI.
For some applications it might be useful starting of jitter attenuation at lower frequencies.
Therefore the corner frequency is switchable by the factor of ten downto 0.2 Hz
(LIM2.SCF).
The DCO-R circuitry is automatically centered to the nominal bit rate if the reference
clock on pin SYNC / RCLK is missed for two 2.048 MHz clock periods. This center
function of DCO-R may be optionally disabled (CMR2.DCF = 1) in order to accept a
gapped reference clock. In analog line interface mode the RCLK is always running. Only
in digital line interface mode with single rail data a gapped clock may occur.
Semiconductor Group
therefore from 16 to 4096 pulse periods. ETS300233 requires detection intervals of at
least 1 ms. This time period results always in a LFA (Loss of Frame Alignment) before
a LOS will be detected.
In general the recovery procedure starts after detecting a logical ‘one’ (digital receive
interface) or a pulse (analog receive interface) with an amplitude more than Q dB
(defined by LIM1.RIL2-0) of the nominal pulse. The value in the 8 bit register PCR
defines the number of pulses (1 to 255) to clear the LOS alarm. Additional recovery
conditions may be programmed by register LIM2.
39
Functional Description E1
PEB 22554
09.98