PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 7

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Quad Frame Aligner
• Frame alignment/synthesis for 2.048 MBit/s according to ITU-T G.704
• Programmable formats : Doubleframe, CRC Multiframe
• CRC4 to Non-CRC4 Interworking of ITU-T G. 706 Annex B
• Error checking via CRC4 procedures according to ITU-T G. 706
• Alarm and performance monitoring per second
• Insertion and extraction of alarms (AIS, Remote Alarm …)
• IDLE code insertion for selectable channels
• Flexible system clock frequency different for receiver and transmitter
• Supports programmable system data rates: 2048 , 4096, 8192 and 16.384MBit/s
• Mux of 4 channels into a single rail 8.192 MBit/s data bus and v.v.
• Elastic store for receive and transmit route clock wander and jitter compensation;
• Programmable elastic buffer size: 2 frames / 1 frame / short buffer / bypass
• Supports fractional E1 access
• Flexible transparent modes
• Programmable In-Band Loop Code detection and generation
• Channel loop back , line loop back or Payload loop back capabilities
• Pseudo Random Bit Sequence (PRBS) generator and monitor
Quad Signaling Controller
• HDLC controller
• CAS controller with last look capability , enhanced CAS- register access and freeze
• Provides access to serial signaling data streams
• Multiframe synchronization and synthesis acc. to ITU-T G.732
• Alarm insertion and detection (AIS and LOS in Timeslot 16)
• Transparent Mode
• FIFO buffers (64 bytes deep) for efficient transfer of data packets.
• Time-slot assignment
• Time-slot 0 SA
Semiconductor Group
16 bit counter for CRC-, framing errors, code violations, error monitoring via E bit and
SA6 bit, errored blocks, PRBS bit errors
with independent receive/transmit offset programming
Bit stuffing, CRC check and generation, flag generation, flag and address recognition,
handling of bit oriented functions
signaling indication
Any combination of time slots selectable for data transfer independent of signaling
mode.
Selectable conditions for recover / loss of frame alignment
with byte - or bitinterleaved formats
controlled slip capability and slip indication;
8-4
bit handling via FIFOs
7
PEB 22554
Features E1
09.98