PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 25

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Pin Definitions and Function (cont’d)
Pin No.
120 - 123
126 - 129
51 - 54
57 - 60
Semiconductor Group
Symbol
XP(A-D)1
XP(A-D)2
XP(A-D)3
XP(A-D)4
Input (I)
Output (O)
I + PU
I + PU
O
O
O
O
Function
Transmit Signaling Data (XSIG)
Enabled with PC(1-4).XPC(2-0) = 010.
Input for transmit signaling data received from
the signaling highway. Optionally (SIC3.TTRF)
sampling of XSIG data is controlled by the
active high XSIGM marker. In higher data rates
sampling of data is defined by bits SIC2.SICS2-
0. In system interface multiplex mode latching
of the datastream containing the 4 signaling
multiframes is done byte or bit interleaved on
port XPC1.
Transmit Clock (TCLK)
Enabled with PC(1-4).XPC(2-0) = 011.
A 2.048 / 8.192 MHz clock has to be sourced by
the system if the internal generated transmit
clock (DCO-X) should not be used. Optional this
input functions as a synchronization clock for
the DCO-X circuitry with a frequency of
2.048 MHz clock.
Transmit Multiframe Begin (XMFB)
XMFB marks the beginning of every transmitted
multiframe (XDI). Active high for one
2.048 MBit/s period. Enabled with PC(1-
4).XPC(2-0) = 100.
Transmit Signaling Marker (XSIGM)
Marks the transmit time-slots which are defined
by register TTR1-4 of every frame transmitted
via port XDI.
Enabled with PC(1-4).XPC(2-0) = 101.
Data Link Bit Transmit (DLX)
Marks the SA8-4 bits within the data stream on
XDI. The SA8-4 bit positions in time-slot 0 of
every frame not containing the frame alignment
signal are selected by register XC0.SA8E-
SA4E. Enabled with PC(1-4).XPC(2-0) = 110.
Transmit Clock (XCLK)
Transmit line clock, frequency: 2.048 MHz
Derived from SCLKX/R, RCLK or internally
generated by the DCO-X circuitry.
Enabled with PC(1-4).XPC(2-0) = 111.
25
Pin Descriptions E1
PEB 22554
09.98