PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 226

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

• Bit Oriented Messages in ESF-DL Channel
• 4 kbit/s Data Link Access in F72 Format
7.5
The QuadFALC offers a flexible feature for system designers where for transmit and
receive direction different system clocks and system pulses are necessary. The interface
to the receive system highway is realized by two data buses, one for the data RDO and
one for the signaling data RSIG. The receive highway is clocked via pin SCLKR, while
the interface to the transmit system highway is independently clocked via pin SCLKX.
The
2.048 / 4.096 / 8.192 / 16.384 / 1.544 / 3.088 / 6.192 / 12.352 MBit/s for the receive and
transmit system interface is programmable by SIC1.SSC1/0, SIC2.SSC2 and
SIC1.SSD1, FMR1.SSD0. Selectable system clock and data rates and their valid
combinations are shown in the table below.
Semiconductor Group
on port FREEZ (RPA-D) and indicated by register SIS.SFS. If SIS.SFS is active
updating of the registers RS1-12 is disabled. Optionally automatic freeze signaling
may be disabled by setting bit SIC3.DAF.
To relieve the µP load from always reading the complete RS1-12 buffer every 3 msec
the QuadFALC notifies the µP via interrupt ISR0.RSC only when signaling changes
from one multiframe to the next. Additionally the QuadFALC generates a receive
signaling data change pointer (RSP1/2) which directly points to the updated RS1-12
register. .
The QuadFALC supports the DL-channel protocol for ESF format according to ANSI
T1.403 specification or according to AT&T TR54016. The HDLC- and Bit Oriented
Message (BOM) -Receiver may be switched ON/OFF independently. If the
QuadFALC is used for HDLC formats only, the BOM receiver has to be switched off.
If HDLC- and BOM-receiver has been switched on (MODE.HRAC/BRAC), an
automatic switching between HDLC and BOM mode is enabled. If eight or more
consecutive ones are detected, the BOM mode is entered. Upon detection of a flag in
the data stream, the QuadFALC switches back to HDLC-mode. In BOM-mode, the
following byte format is assumed (the left most bit is received first).
111111110xxxxxx0
Three different BOM reception modes may be programmed (CCR1.BRM+
CCR2.RBFE). If CCR2.RFBE is set, the BOM-receiver will only accept BOM frames
after detecting 7 out of 10 equal BOM pattern. Buffering of receive data is done in a 64
byte deep RFIFO. Refer also to chapter 8.1.4
The DL-channel protocol is supported as follows:
- access is done on a multiframe basis via registers RDL1-3,
- the DL bit information from frame 26 to 72 is stored in the Receive FIFO of the
signaling controller.
frequency
System Interface
of
these
working
226
clocks
Functional Description T1 / J1
and
the
data
PEB 22554
rate
09.98
of