PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 205

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

7.2
The communication between the CPU and the QuadFALC is done via a set of directly
accessible registers. The interface may be configured as Siemens/Intel or Motorola type
with a selectable data bus width of 8 or 16 bits.
The CPU transfers data to/from the QuadFALC (via 64 byte deep FIFOs per direction
and channel), sets the operating modes, controls function sequences, and gets status
information by writing or reading control/status registers. All accesses can be done as
byte or word accesses if enabled. If 16-bit bus width is selected, access to lower/upper
part of the data bus is determined by address line A0 and signal BHE/BLE as shown in
table 13 and 14.
In table chapter Table 15 is shown how the ALE (address latch enable) line is used to
control the bus structure and interface type. The switching of ALE allows the QuadFALC
to be directly connected to a multiplexed address/data bus.
Mixed Byte/Word Access to the FIFOs
Reading from or writing to the internal FIFOs (RFIFO and XFIFO of each channel) can be
done using a 8-bit (byte) or 16-bit (word) access depending on the selected bus interface
mode. Randomly mixed byte/word access to the FIFOs is allowed without any
restrictions.
Table 13
Data Bus Access (16-Bit Intel Mode)
BHE
0
0
1
1
Semiconductor Group
Microprocessor Interface
A0
0
1
0
1
Register Access
FIFO word access
Register word access (even addresses)
Register byte access (odd addresses)
Register byte access (even addresses)
No transfer performed
205
Functional Description T1 / J1
QuadFALC Data Pins
Used
D0 – D15
D8 – D15
D0 – D7
None
PEB 22554
09.98