PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 278

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Table 28
Configuration if Initialized after RESET (cont’d)
Register
RC0
RC1
IDLE
ICB 1
CCB 1
LIM0
LIM1
PCD
PCR
XPM2-0
IMR1-4
GCR
CMR1
CMR2
GPC1
PC1-4
PC5
RTR1-4
TTR1-4
MODE
RAH1/2
RAL1/2
Semiconductor Group
3
3
Initiated
Value
00
00
00
00
00
00
00
00
00
00,03,9c
FF
00
00
00
00
00
00
00
00
00
FD
FF
H
H
H
H
H
H
H
H
H
H
H
H
H
H ,
H ,
H
H
H
H
H
H
,FF
,FF
00
00
H
H
H
H
H
Meaning
The receive clock slot offset is cleared.
The receive time-slot offset is cleared.
Idle channel code is cleared.
Normal operation (no “Idle Channels” selected).
Normal operation (no clear channel operation).
Slave Mode, Local Loop off,
Analog interface selected, Remote Loop off
Pulse Count for LOS Detection cleared
Pulse Count for LOS Recovery cleared
Transmit Pulse Mask
All interrupts are disabled
Internal second timer, Power on of all 4 single FALC
channels,
DCO-R reference clock: channel 1, RCLK output: DPLL
clock, DCO-X enabled, DCO-X internal reference clock
SCLKR selected, SCLKX selected, Rec. synchr. pulse
sourced by SYPR, Tr. synchr. pulse sourced by SYPX,
system multiplex mode disabled, SEC port input active
high, FSC is sourced by channel 1, RCLK1 clock source:
channel 1,
Input function of ports RP(A-D) : SYPR,
Input function of ports XP(A-D) : SYPX
SCLKR, SCLKX, RCLK configured to inputs,
XMFS active low
No time-slots selected
Signaling controller disabled
Compare register for receive address cleared
278
Operational Description T1 / J1
PEB 22554
09.98