PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 323

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Clock Mode Register 1 (Read/Write)
Value after RESET: 00
CMR1
DRSS1 ... 0 …
RS1 ... 0 …
DCS …
Semiconductor Group
7
DRSS1
DRSS0
1…
DCO-R Synchronization Clock Source
These bits select the reference clock source for the DCO-R circuitry.
00… receive reference clock generated by the DPLL of channel 1
01… receive reference clock generated by the DPLL of channel 2
10… receive reference clock generated by the DPLL of channel 3
11… receive reference clock generated by the DPLL of channel 4
Note: After Reset all DCO-R circuitries will synchronize on the clock
Select RCLK Source
These bits select the source of RCLK.
00… extracted receive clock, generated by the DPLL
01… extracted receive clock with the option in case of an active LOS
10… dejittered 1.544 or 2.048 MHz clock generated by the internal
11… dejittered 6.176 or 8.192 MHz clock generated by the internal
Disable Clock Switching
In Slave mode (LIM0.MAS = 0) the DCO-R is synchronized on the
recovered route clock. In case of loss of signal LOS the DCO-R
H
Automatic freezing of signaling data is disabled. Updating of the
signaling buffer is also done if one of the above described alarm
conditions is active. However, updating of the signaling buffer is
stopped if SIC2.FFS is set. Significant only if the serial signaling
access is enabled.
alarm this pin is set high.
DCO-R circuitry. The frequency depends on SIC2.SSC2.
DCO-R circuitry. The frequency depends on SIC2.SSC2.
sourced by the DPLL of channel 1 . Each channel have to be
configured individually.
If LIM0.MAS is set the DCO-R circuitry will synchronize on the
clock applied to port SYNC.
RS1
RS0
323
DCS
Operational Description T1 / J1
STF
DXJA
0
DXSS
PEB 22554
(x44)
09.98