PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 140

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Clock Mode Register 2 (Read/Write)
Value after RESET: 00
CMR2
DCF …
IRSP …
IRSC …
Semiconductor Group
7
Internal Receive System Frame Sync Pulse
Internal Receive System Clock
1…
DCO-R Center- Frequency Disabled
0…
1…
0…
1…
Only applicable if bit GPC1.SMM is cleared. If GPC1.SMM is set
SCLKR1 of channel 1 provides the working clock for all four channels.
H
DCO-X synchronizes to an external reference clock provided by
The DCO-R circuitry may be frequency centered
The center function of the DCO-R circuitry is disabled. The
The frame sync pulse for the receive system interface is
The frame sync pulse for the receive system interface is
pin XP(A-D) pin function TCLK, if no remote loop is active.
TCLK is selected by PC(1-4).XPC(2-0) = 011.
- in master mode if no reference clock on pin SYNC is provided
or
- in slave mode if a loss of signal occurs in combination with no
clock on pin SYNC or
- a gapped clock is provided at pin RCLKI and this clock is
inactive or stopped.
generated clock (DCO-R) is frequency frozen in that moment
when no clock is available at pin SYNC or pin RCLKI. The
DCO-R circuitry will starts synchronization as soon as a clock at
pins SYNC or RCLKI appears.
sourced by SYPR.
internally sourced by the DCO-R circuitry of each channel. This
internally generated frame sync could be output active low on
pin RP(A-D). RPC(2-0) = 001. Programming the receive time-
slot offset is also done in the same way as it is done for the
external SYPR. For correct operation bit IRSC must be set.
SYPR is ignored.
DCF
140
IRSP
IRSC
Operational Description E1
IXSP
0
IXSC
PEB 22554
(x45)
09.98