PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 324

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

STF …
DXJA…
DXSS …
Clock Mode Register 2 (Read/Write)
Value after RESET: 00
CMR2
DCF …
Semiconductor Group
7
switches automatically to the clock sourced by port SYNC. Setting
this bit automatic switching from RCLK to SYNC is disabled.
Select TCLK Frequency
Only applicable if the pin function TCLK port XP(A-D) is selected by
PC(1-4).XPC(2-0) = 011. Data on XL1/2 , XDOP/N, XOID are clocked
off with TCLK.
0…
1…
Disable Internal Transmit Jitter Attenuation
Setting this bit disables the transmit jitter attenuation. Reading the
data out of the transmit elastic buffer and transmitting on XL1/2
(XDOP/N / XOID) is done with the clock provided on pin TCLK. In
transmit elastic buffer bypass mode the transmit clock is taken from
SCLKX, independent of this bit.
DCO-X Synchronization Clock Source
0…
1…
DCO-R Center- Frequency Disabled
0…
H
1.544 MHz
6.176 MHz
The DCO-X circuitry of each channel will synchronize to the
DCO-X synchronizes to an external reference clock provided by
The DCO-R circuitry may be frequency centered
internal reference clock which is sourced by SCLKX/R or
RCLK. Since there are many reference clock opportunities the
following internal priorization in descenting order from left to
right is realized: LIM1.RL > CMR2.DXSS > LIM2.ELT > current
working clock of transmit system interface.
If one of these bits is set the corresponding reference clock is
taken.
pin XP(A-D) pin function TCLK, if no remote loop is active.
TCLK is selected by PC(1-4).XPC(2-0) = 011.
- in master mode if no reference clock on pin SYNC is provided
or
- in slave mode if a loss of signal occurs in combination with no
DCF
324
IRSP
Operational Description T1 / J1
IRSC
IXSP
0
IXSC
PEB 22554
(x45)
09.98