PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 358

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

RPF…
Interrupt Status Register 1 (Read)
ISR1
All bits are reset when ISR1 is read.
If bit GCR.VIS is set to ‘1’, interrupt statuses in ISR1 may be flagged although they are
masked via register IMR1. However, these masked interrupt statuses neither generate a
signal on INT, nor are visible in register GIS.
CASE…
RDO…
ALLS…
XDU…
Semiconductor Group
7
CASE
Receive Pool Full
32 bytes of a frame have arrived in the receive FIFO. The frame is not
yet completely received.
Transmit CAS Register Empty
In ESF format this bit is set with the beginning of a transmitted
multiframe related to the internal transmitter timing. In F12 + F72
format this interrupt will occur every 24 frames to inform the user that
new bit robbing data has to written to XS1-12 registers. This interrupt
will only be generated if the serial signaling access on the system
highway is not enabled.
Receive Data Overflow
This interrupt status indicates that the CPU does not respond quickly
enough to an RPF or RME interrupt and that data in RFIFO has been
lost. Even when this interrupt status is generated, the frame continues
to be received when space in the RFIFO is available again.
Note: Whereas the bit RSIS.RDO in the frame status byte indicates
All Sent
This bit is set if the last bit of the current frame is completely sent out
and XFIFO is empty.
Transmit Data Underrun
Transmitted frame was terminated with an abort sequence because
no data was available for transmission in XFIFO and no XME was
issued.
RDO
whether an overflow occurred when receiving the frame
currently accessed in the RFIFO, the ISR1.RDO interrupt
status is generated as soon as an overflow occurs and does
not necessarily pertain to the frame currently accessed by the
processor.
ALLS
XDU
358
XMB
Operational Description T1 / J1
XLSC
0
XPR
PEB 22554
(x69)
09.98