PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 297

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

CRC…
ECM…
SSD0…
Semiconductor Group
0…
1…
Enable CRC6
This bit is only significant when using the ESF format.
0
1
Error Counter Mode
The function of the error counters (FEC,CEC,CVC,EBC) will be
determined by this bit.
0
1…
Select System Date Rate 0
SIC1.SSD1, FMR1.SSD0 and SIC2.SSC2 define the data rate on the
system highway. Programming SSD1/SSD0 and corresponding data
rate is shown below.
SIC2.SSC2 = 0:
SIC2.SSC2 = 1:
PCM 30 or E1 mode.
PCM 24 or T1 mode.
CRC6 check/generation disabled. For transmit direction, all
CRC bit positions are set to ‘1’.
CRC6 check/generation enabled.
Before reading an error counter the corresponding bit in the
Disable Error Counter register (DEC) has to be set. In 8 bit
access the low byte of the error counter should always be read
before the high byte. The error counters will be reset with the
rising edge of the corresponding bits in the DEC register.
Every second the error counter will be latched and then
automatically be reset. The latched error counter state should
be read within the next second. Reading the error counter
during updating should be avoided.
00…2.048 MBit/s
01…4.096 MBit/s
10…8.192 MBit/s
11…16.384 MBit/s
00…1.544 MBit/s
01…3.088 MBit/s
10…6.176 MBit/s
11…12.352 MBit/s
297
Operational Description T1 / J1
PEB 22554
09.98