PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 168

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Receive Sa6-Bit Status (Read)
RSA6S
S_X…
S_F…
S_E…
S_C…
S_A…
Semiconductor Group
7
Receive Sa6-Bit Status: “1100”
Receive Sa6-Bit Status: “1010”
Four consecutive received SA6-bits are checked on the by ETS
300233 defined SA6-bit combinations. The QuadFALC will detect the
following “fixed” SA6-bit combinations:
SA61,SA62,SA63,SA64=1000; 1010; 1100; 1110; 1111. All other
possible 4 bit combinations are grouped to status “X”.
A valid SA6-bit combination must occur three times in a row. The
corresponding status bit in this register will be set. Even if the
detected status will be active for a short time the status bit remains
active until this register is read. Reading the register will reset all
pending status information.
With any change of state of the SA6-bit combinations an interrupt
status ISR0.SA6SC will be generated.
During the basicframe asynchronous state updating of this register
and interrupt status ISR0.SA6SC is disabled. In multiframe format the
detection of the SA6-bit combinations can be done either
synchronous or asynchronous to the submultiframe (FMR3.SA6SY).
In synchronous detection mode updating of register RSA6S is done
in the multiframe synch. state (FRS0.LMFA=0). In asynchr. detection
mode updating is independent to the multiframe synchronous state.
Receive Sa6-Bit Status_X
If none of the fixed SA6-bit combinations are detected this bit will be
set.
Receive Sa6-Bit Status: “1111”
Receive SA6-bit status “1111” is detected for three times in a row in
the SA6-bit positions.
Receive Sa6-Bit Status: “1110”
Receive SA6-bit status “1110” is detected for three times in a row in
the SA6-bit positions.
Receive SA6-bit status “1100” is detected for three times in a row in
the SA6-bit positions.
S_X
S_F
168
S_E
S_C
Operational Description E1
S_A
0
S_8
PEB 22554
(x61)
09.98