PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 286

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

XRES…
XHF…
XTF…
XME…
SRES…
Mode Register (Read/Write)
Value after RESET: 00
Semiconductor Group
MODE
7
MDS2
Transmitter Reset
The transmit framer and transmit line interface excluding the system
clock generator and the pulse shaper will be reset. However the
contents of the control registers will not be deleted.
Transmit HDLC Frame
After having written up to 32 bytes to the XFIFO, this command
initiates the transmission of a HDLC frame.
Transmit Transparent Frame
Initiates the transmission of a transparent frame without HDLC
framing.
Transmit Message End
Indicates that the data block written last to the transmit FIFO
completes the current frame. The QuadFALC can terminate the
transmission operation properly by appending the CRC and the
closing flag sequence to the data.
Signaling Transmitter Reset
The transmitter of the signaling controller will be reset. XFIFO is
cleared of any data and an abort sequence (seven 1’s) followed by
interframe time fill is transmitted. In response to XRES an XPR
interrupt is generated.
This command can be used by the CPU to abort a frame currently in
transmission.
Note: The maximum time between writing to the CMDR register and
MDS1
H
the execution of the command takes 2.5 periods of the current
system data rate. Therefore, if the CPU operates with a very
high clock rate in comparison with the QuadFALC’s clock, it is
recommended that bit SIS.CEC should be checked before
writing to the CMDR register to avoid any loss of commands.
MDS0
BRAC
286
HRAC
Operational Description T1 / J1
DIV
0
PEB 22554
(x03)
09.98