PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 158

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

TS16AIS…
TS16LFA…
XLS…
XLO…
Semiconductor Group
Receive Timeslot 16 Alarm Indication Signal
The detection of the alarm indication signal in timeslot 16 is according
to ITU-T G.775.
This bit is set if the incoming TS16 contains less than 4 zeros in each
of two consecutive TS16 multiframe periods. This bit will be cleared if
two consecutive received CAS multiframe periods contains more than
3 zeros or the multiframe pattern was found in each of them. This bit
will be cleared if TS0 synchronization is lost.
Receive Timeslot 16 Loss of Multiframe Alignment
1 ... This bit is set if the framing pattern ‘0000’ in 2 consecutive CAS
Transmit Line Short
Significant only if the ternary line interface is selected by
LIM1.DRS=0.
0…
Transmit Line Open
0…
0 ... The CAS controller is in synchronous state after frame
1… The XL1 and XL2 are shortend for at least 3 pulses. As a
1… This bit will be set if at least 32 consecutive zeros were sent via
alignment is accomplished.
multiframes were not found or in all TS16 of the preceding
multiframe all bits were reset. An interrupt ISR3.LMFA16 will be
generated.
Normal operation. No short is detected.
reaction of the short the pins XL1 and XL2 are automatically
forced into a high impedance state if bit XPM2.DAXLT is reset.
After 128 consecutive pulse periods the outputs XL1/2 are
activated again and the internal transmit current limiter is
checked. If a short between XL1/2 is still further active the
outputs XL1/2 are in high impedance state again. When the
short disappears pins XL1/2 are activated automatically and
this bit will be reset. With any change of this bit an interrupt
ISR1.XLSC will be generated. In case of XPM2.XLT is set this
bit will be frozen.
Normal operation
pins XL1/XL2 resp. XDOP/XDON. This bit is reset with the first
transmitted pulse. With the rising edge of this bit an interrupt
ISR1.XLSC will be set. In case of XPM2.XLT is set this bit will
be frozen.
158
Operational Description E1
PEB 22554
09.98