PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 211

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

TAP controller into test logic reset state.
of the boundary scan. Both, TAP controller and boundary scan, meet the requirements
given by the JTAG standard: IEEE 1149.1. Figure 42 gives an overview.
Figure 42
Block Diagram of Test Access Port and Boundary Scan
Test handling is performed via the pins TCK (Test Clock), TMS (Test Mode Select), TDI
(Test Data Input) and TDO (Test Data Output). Test data at TDI are loaded with a 4-MHz
clock signal connected to TCK. ‘1’ or ‘0’ on TMS causes a transition from one controller
state to an other; constant ’1’ on TMS leads to normal operation of the chip.
If no boundary scan testing is planned TMS and TDI do not need to be connected since
pull-up transistors ensure high input levels in this case. Nevertheless it would be a good
practice to put the unused inputs to defined levels. In this case, if the JTAG is not used:
TMS = TCK = ‘1’.
After switching on the device (
Semiconductor Group
TMS
TDO
TRS
TCK
TDI
CLOCK
Test
Control
Data IN
TAP Controller Reset
Enable
Data OUT
Test Access Port
Generation
Clock
-Finite State Machine
-Instruction Register (3 bits)
-Test Signal Generator
V
DD
CLOCK
TAP Controller
= 0 to 3.3 V) pin TRS has to reset which forces the
211
Reset
Reset
Functional Description T1 / J1
BS Data IN
Control Bus
ID Data OUT
SS Data OUT
6
PEB 22554
1
2
n
ITB10938
Pins
09.98