PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 84

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Alarm Simulation
Alarm simulation does not affect the normal operation of the device, i.e. all time-slots
remain available for transmission. However, possible ‘real’ alarm conditions are not
reported to the processor or to the remote end when the device is in the alarm simulation
mode.
The alarm simulation is initiated by setting the bit FMR0.SIM. The following alarms are
simulated:
• Loss of Signal
• Alarm Indication Signal (AIS)
• Loss of pulse frame
• Remote alarm indication
• Receive and transmit slip indication
• Framing error counter
• Code violation counter (HDB3 Code)
• CRC4 error counter
• E-Bit error counter
• CEC2 counter
• CEC3 counter
Some of the above indications are only simulated if the QuadFALC is configured in a
mode where the alarm is applicable (e.g. no CRC4 error simulation when doubleframe
format is enabled).
– Setting of the bit FMR0.SIM initiates alarm simulation, interrupt status bits will be set.
Semiconductor Group
Error counting and indication will occurs while this bit is set. After it is reset all
simulated error conditions disappear, but the generated interrupt statuses are still
pending until the corresponding interrupt status register is read. Alarms like AIS and
LOS are cleared automatically. Interrupt status register and error counters are
automatically cleared on read.
84
Functional Description E1
PEB 22554
09.98