PEB22554 SIEMENS [Siemens Semiconductor Group], PEB22554 Datasheet - Page 58

• Manufacturer Part Number: PEB22554
• Description: ICs for Communications
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Transmit Signaling Controller
Similar to the receive signaling controller the same signaling methods and the same
time-slot assignment is provided. The QuadFALC will perform the following signaling and
data link methods:
• HDLC or LAPD access
• S
• Channel Associated Signaling CAS
If the QuadFALC is optioned for no signaling, the data stream from the system interface
will pass the QuadFALC undisturbed.
Semiconductor Group
The transmit signaling controller of the QuadFALC performs the FLAG generation,
CRC generation, zero bit-stuffing and programmable IDLE code generation. Buffering
of transmit data is done in the 64 byte deep XFIFO. The signaling information will be
internally multiplexed with the data applied to port XDI or XSIG.
In signaling controller transparent mode, fully transparent data transmission without
HDLC framing is performed. Optionally the QuadFALC supports the continuous
transmission of the XFIFO contents.
The QuadFALC offers the flexibility to insert data during certain time-slots. Any
combinations of time-slots may be programmed separately for the receive and
transmit directions.
The QuadFALC supports the S
follows:
- the access via registers XSW
- the access via registers XSA8-4, capable of storing the information for a complete
multiframe
- the access via the 64 byte deep XFIFO of the signaling controller. This S
gives the opportunity to transparent a bit stream as well as HDLC frames where the
signaling controller automatically processes the HDLC protocol. Any combination of
S
XC0.SA8-4.
Transmit data stored in registers XS1-16 will transmitted on a multiframe boundary in
time-slot 16. The signaling controller inserts the bit stream either on the transmit line
side or if external signaling is enabled on the transmit system side via pinfunction
XSIG, which is selected by register PC1-4.
In external signaling mode the signaling data is received at port XSIG. The signaling
data is sampled with the working clock of the transmit system interface (SCLKX) in
conjunction with the transmit synchron. pulse (SYPX). Data on XSIG will be latched in
the bit positions 5-8 per time-slot, bits 1-4 will be ignored. Time-slot 0 and 16 are
sampled completly (bit 1-8). The received CAS multiframe will be inserted frame
aligned into the data stream on XDI. Data sourced by the internal signaling controller
will overwrite the external signaling data.
a
a
bit Access
bits which should be inserted in the outgoing data stream may be selected by
a
bit signaling of time-slot 0 of every other frame as
58
Functional Description E1
PEB 22554
a
bit access
09.98