R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 970

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 25 List of Registers
Register Name
Timer interrupt enable register_1
Timer status register_1
Timer counter_1
Timer general register A_1
Timer general register B_1
Timer control register_2
Timer mode register_2
Timer I/O control register_2
Timer interrupt enable register_2
Timer status register_2
Timer counter_2
Timer general register A_2
Timer general register B_2
Timer control register_3
Timer mode register_3
Timer I/O control register H_3
Timer I/O control register L_3
Timer interrupt enable register_3
Timer status register_3
Timer counter_3
Timer general register A_3
Timer general register B_3
Timer general register C_3
Timer general register D_3
Note:
Rev. 2.00 Sep. 16, 2009 Page 940 of 1036
REJ09B0414-0200
*
When the same output trigger is specified for pulse output groups 2 and 3 by the PCR
setting, the NDRH address is H'FFF7C. When different output triggers are specified, the
NDRH addresses for pulse output groups 2 and 3 are H'FFF7E and H'FFF7C,
respectively. Similarly, when the same output trigger is specified for pulse output groups
0 and 1 by the PCR setting, the NDRL address is H'FFF7D. When different output
triggers are specified, the NDRL addresses for pulse output groups 0 and 1 are
H'FFF7F and H'FFF7D, respectively.
Abbreviation
TIER_1
TSR_1
TCNT_1
TGRA_1
TGRB_1
TCR_2
TMDR_2
TIOR_2
TIER_2
TSR_2
TCNT_2
TGRA_2
TGRB_2
TCR_3
TMDR_3
TIORH_3
TIORL_3
TIER_3
TSR_3
TCNT_3
TGRA_3
TGRB_3
TGRC_3
TGRD_3
Number
of Bits
8
8
16
16
16
8
8
8
8
8
16
16
16
8
8
8
8
8
8
16
16
16
16
16
H'FFFD4
H'FFFD5
H'FFFD6
H'FFFD8
H'FFFE1
H'FFFE2
H'FFFE4
H'FFFE6
H'FFFF1
H'FFFF2
H'FFFF3
H'FFFF4
H'FFFF6
Address
H'FFFDA
H'FFFE0
H'FFFE5
H'FFFE8
H'FFFEA
H'FFFF0
H'FFFF5
H'FFFF8
H'FFFFA
H'FFFFC
H'FFFFE
Module
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
Data
Width
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Access
Cycles
(Read/Write)
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ