R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 706

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 Serial Communication Interface (SCI)
16.9.5
The TDRE flag in SSR is a status flag which indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR irrespective of the TDRE flag status. However, if new data is written
to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR
yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the
TDRE flag is set to 1.
16.9.6
• When the external clock source is used as a synchronization clock, update TDR by the DTC or
• When using the DTC or DMAC to read RDR, be sure to set the receive end interrupt (RXI) as
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REJ09B0414-0200
DMAC and wait for at least five Pφ clock cycles before allowing the transmit clock to be
input. If the transmit clock is input within four clock cycles after TDR modification, the SCI
may malfunction (figure 16.33).
the DTC or DMAC activation source.
Figure 16.33 Sample Transmission using DTC in Clocked Synchronous Mode
Relation between Writing to TDR and TDRE Flag
Restrictions on Using DTC or DMAC
SCK
TDRE
Serial data
Note: When external clock is supplied, t must be more than four clock cycles.
t
LSB
D0
D1
D2
D3
D4
D5
D6
D7