R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 216

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Bus Controller (BSC)
Rev. 2.00 Sep. 16, 2009 Page 186 of 1036
REJ09B0414-0200
Name
Chip select 0
Chip select 1
Chip select 2
Chip select 3
Chip select 4
Chip select 5
Chip select 6
Chip select 7
Wait
Bus request
Bus request
acknowledge
Bus request output
Data transfer
acknowledge 1
(DMAC_1)
Data transfer
acknowledge 0
(DMAC_0)
External bus clock
Symbol
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
WAIT
BREQ
BACK
BREQO
DACK1
DACK0
Bφ
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Output
Output
Output
Output
Output
I/O
Function
Strobe signal indicating that area 0 is selected
Strobe signal indicating that area 1 is selected
Strobe signal indicating that area 2 is selected
Strobe signal indicating that area 3 is selected
Strobe signal indicating that area 4 is selected
Strobe signal indicating that area 5 is selected
Strobe signal indicating that area 6 is selected
Strobe signal indicating that area 7 is selected
Wait request signal when accessing external
address space.
Request signal for release of bus to external bus
master
Acknowledge signal indicating that bus has been
released to external bus master
External bus request signal used when internal bus
master accesses external address space in the
external-bus released state
Data transfer acknowledge signal for DMAC_1
single address transfer
Data transfer acknowledge signal for DMAC_0
single address transfer
External bus clock