R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 169

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.8
6.8.1
When an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request with priority
over that interrupt, interrupt exception handling will be executed for the interrupt with priority,
and another interrupt will be ignored. The same also applies when an interrupt source flag is
cleared to 0. Figure 6.7 shows an example in which the TCIEV bit in TIER of the TPU is cleared
to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
Similarly, when an interrupt is requested immediately before the DTC enable bit is changed to
activate the DTC, DTC activation and the interrupt exception handling by the CPU are both
executed. When changing the DTC enable bit, make sure that an interrupt is not requested.
Pφ
Internal
address bus
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Usage Notes
Conflict between Interrupt Generation and Disabling
Figure 6.7 Conflict between Interrupt Generation and Disabling
TIER_0 write cycle by CPU
TIER_0 address
Rev. 2.00 Sep. 16, 2009 Page 139 of 1036
TCIV exception handling
Section 6 Interrupt Controller
REJ09B0414-0200