R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 955

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 24 Power-Down Modes
24.12
Usage Notes
24.12.1 I/O Port Status
In software standby mode or deep software standby mode, the I/O port states are retained.
Therefore, there is no reduction in current drawn due to output currents when high-level signals
are being output.
24.12.2 Current Consumption during Oscillation Settling Standby Period
Current consumption increases during the oscillation settling standby period.
24.12.3 Module Stop State of DMAC or DTC
Depending on the operating state of the DMAC and DTC, bits MSTPA13 and MSTPA12 may not
be set to 1, respectively. The module stop state setting for the DMAC or DTC should be carried
out only when the DMAC or DTC is not activated.
For details, refer to section 9, DMA Controller (DMAC), and section 10, Data Transfer Controller
(DTC).
24.12.4 On-Chip Peripheral Module Interrupts
Relevant interrupt operations cannot be performed in a module stop state. Consequently, if module
stop state is entered when an interrupt has been requested, it will not be possible to clear the CPU
interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled
before entering a module stop state.
24.12.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC
MSTPCRA, MSTPCRB, and MSTPCRC should only be written to by the CPU.
Rev. 2.00 Sep. 16, 2009 Page 925 of 1036
REJ09B0414-0200