R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 907

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.3
The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 4. The frequency multiplication factor is fixed. The phase difference is controlled so that
the timing of the rising edge of the internal clock is the same as that of the EXTAL pin signal.
23.4
23.4.1
The frequency divider divides the PLL clock to generate a 1/2, 1/4, or 1/8 clock. After bits ICK2
to ICK0, PCK 2 to PCK0, and BCK2 to BCK0 are modified, this LSI operates at the modified
frequency.
23.4.2
The frequency divider divides the frequency of the PLL clock to create 1/3, 1/4, 1/5, and 1/6
clocks. After the ACK2, ACK1, and ACK0 bits are rewritten, the ∆Σ A/D converter operates
according to the frequency available after change. Before rewriting these bits, you need to set the
∆Σ A/D converter's module stop bit to 1 so that the ∆Σ A/D converter is stopped. Setting this
frequency is recommended because of the characteristics of the ∆Σ A/D converter: that is, Aφ is
designed to produce maximum accuracy in the neighborhood of 25 MHz.
PLL Circuit
Frequency Divider
1φ, Bφ, Pφ Frequency Dividers
Aφ Frequency Divider
Rev. 2.00 Sep. 16, 2009 Page 877 of 1036
Section 23 Clock Pulse Generator
REJ09B0414-0200