R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 377

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.2.7
DTCER, which is comprised of eight registers, DTCERA to DTCERH, is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 10.1. Use bit manipulation instructions such as BSET and BCLR to read or write a
DTCE bit. If all interrupts are masked, multiple activation sources can be set at one time (only at
the initial setting) by writing data after executing a dummy read on the relevant register.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Name
DTCE15
DTCE14
DTCE13
DTCE12
DTCE11
DTCE10
DTCE9
DTCE8
DTCE7
DTCE6
DTCE5
DTCE4
DTCE3
DTCE2
DTCE1
DTCE0
DTC enable registers A to H (DTCERA to DTCERH)
DTCE15
DTCE7
R/W
R/W
15
0
7
0
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DTCE14
DTCE6
R/W
R/W
14
0
6
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DTCE13
DTCE5
R/W
R/W
13
0
5
0
Description
DTC Activation Enable 15 to 0
Setting this bit to 1 specifies a relevant interrupt source to
a DTC activation source.
[Clearing conditions]
•
•
•
These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not ended
When writing 0 to the bit to be cleared after reading 1
When the DISEL bit is 1 and the data transfer has
ended
When the specified number of transfers have ended
DTCE12
DTCE4
R/W
R/W
12
0
4
0
DTCE11
DTCE3
R/W
R/W
11
0
3
0
Rev. 2.00 Sep. 16, 2009 Page 347 of 1036
Section 10 Data Transfer Controller (DTC)
DTCE10
DTCE2
R/W
R/W
10
0
2
0
DTCE9
DTCE1
R/W
R/W
9
0
1
0
REJ09B0414-0200
DTCE8
DTCE0
R/W
R/W
8
0
0
0