R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 908

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 23 Clock Pulse Generator
23.5
23.5.1
1. The following points should be noted since the frequency of φ (Iφ: system clock, Pφ:
2. All the on-chip peripheral modules (except for the DMAC and DTC) operate on the Pφ.
3. The relationship among the system clock, peripheral module clock, and external bus clock is Iφ
4. Figure 23.6 shows the clock modification timing. After a value is written to SCKCR, this LSI
Rev. 2.00 Sep. 16, 2009 Page 878 of 1036
REJ09B0414-0200
peripheral module clock, Bφ: external bus clock) supplied to each module changes according
to the setting of SCKCR.
Select a clock division ratio that is within the operation guaranteed range of clock cycle time
t
The setting should be within the operation guaranteed range of 8 MHz ≤ Iφ ≤ 50 MHz, 8 MHz
≤ Pφ ≤ 35 MHz, and 8 MHz ≤ Bφ ≤ 50 MHz.
Therefore, note that the time processing of modules such as a timer and SCI differs before and
after changing the clock division ratio.
In addition, wait time for clearing software standby mode differs by changing the clock
division ratio. For details, see section 24.7.3, Setting Oscillation Settling Time after Exit from
Software Standby Mode.
≥ Pφ and Iφ ≥ Bφ. In addition, the system clock setting has the highest priority. Accordingly,
Pφ or Bφ may have the frequency set by bits ICK2 to ICK0 regardless of the settings of bits
PCK2 to PCK0 or BCK2 to BCK0.
waits for the current bus cycle to complete. After the current bus cycle completes, each clock
frequency will be modified within one cycle (worst case) of the external input clock φ.
cyc
shown in the AC timing of electrical characteristics.
Usage Notes
Notes on Clock Pulse Generator