R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 275

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(6)
Depending on the system's load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 8.42. In this case, with the setting for no idle cycle insertion (a), there
may be a period of overlap between the RD signal in bus cycle A and the CS signal in bus cycle B.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals. In the initial state after reset release, idle cycle indicated in (b) is set.
Bφ
Address bus
CS (area A)
CS (area B)
RD
Relationship between Chip Select (CS) Signal and Read (RD) Signal
Figure 8.42 Relationship between Chip Select (CS) and Read (RD)
(a) No idle cycle inserted
Overlap time may occur between the
CS (area B) and RD
T
Bus cycle A
1
(IDLS1 = 0)
T
2
T
3
Bus cycle B
T
1
T
2
(IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)
Rev. 2.00 Sep. 16, 2009 Page 245 of 1036
T
Bus cycle A
1
(b) Idle cycle inserted
T
2
Section 8 Bus Controller (BSC)
T
3
T
i
Bus cycle B
REJ09B0414-0200
T
1
T
2