R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 854

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 22 Flash Memory
22.8.4
In the descriptions in this manual, the on-chip programs and program data storage areas are
assumed to be in the on-chip RAM. However, they can be executed from part of the flash memory
which is not to be programmed or erased as long as the following conditions are satisfied.
• The on-chip program is downloaded to and executed in the on-chip RAM specified by
• Since the on-chip program uses a stack area, allocate 128 bytes at the maximum as a stack
• Download requested by setting the SCO bit in FCCS to 1 should be executed from the on-chip
• In an operating mode in which the external address space is not accessible, such as single-chip
• The flash memory is not accessible during programming/erasure. Programming/erasure is
• After programming/erasure starts, access to the flash memory should be inhibited until FKEY
• Switching of the memory MATs by FMATS should be needed when programming/erasure of
• When the program data storage area is within the flash memory area, an error will occur even
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FTDAR. Therefore, this on-chip RAM area is not available for use.
area.
RAM because it will require switching of the memory MATs.
mode, the required procedure programs, NMI handling vector table, and NMI handling routine
should be transferred to the on-chip RAM before programming/erasure starts (download result
is determined).
executed by the program downloaded to the on-chip RAM. Therefore, the procedure program
that initiates operation, the NMI handling vector table, and the NMI handling routine should be
stored in the on-chip RAM other than the flash memory.
is cleared. The reset input state (period of RES = 0) must be set to at least 100 µs when the
operating mode is changed and the reset start executed on completion of programming/erasure.
Transitions to the reset state are inhibited during programming/erasure. When the reset signal
is input, a reset input state (period of RES = 0) of at least 100 µs is needed before the reset
signal is released.
the user MAT is operated in user boot mode. The program which switches the memory MATs
should be executed from the on-chip RAM. For details, see section 22.11, Switching between
User MAT and User Boot MAT. Make sure you know which memory MAT is currently
selected when switching them.
when the data stored is normal program data. Therefore, the data should be transferred to the
on-chip RAM to place the address that the FMPDR parameter indicates in an area other than
the flash memory.
On-Chip Program and Storable Area for Program Data