R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 816

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 22 Flash Memory
There are several operating modes for accessing the flash memory. Respective operating modes,
registers, and parameters are assigned to the user MAT and user boot MAT. The correspondence
between operating modes and registers/parameters for use is shown in table 22.3.
Table 22.3 Registers/Parameters and Target Modes
Notes: 1. The setting is required when programming or erasing the user MAT in user boot mode.
22.7.1
The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes.
These registers are initialized by a reset.
(1)
FCCS monitors errors during programming/erasing the flash memory and requests the on-chip
program to be downloaded to the on-chip RAM.
Rev. 2.00 Sep. 16, 2009 Page 786 of 1036
REJ09B0414-0200
Register/Parameter
Programming/
erasing interface
registers
Programming/
erasing interface
parameters
RAM emulation
Flash Code Control/Status Register (FCCS)
2. The setting may be required according to the combination of initiation mode and read
Programming/Erasing Interface Registers
target memory MAT.
FCCS
FPCS
FECS
FKEY
FMATS
FTDAR
DPFR
FPFR
FPEFEQ 
FMPAR
FMPDR
FEBS
RAMER
Down-
load
O
O
O
O
O
O
Initiali-
zation
O
O
Program-
ming
O
O*
O
O
O
1
Erasure
O
O*
O
O
1
Read
O*
2
RAM
Emulation
O

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