R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 13

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.4
4.5
4.6
4.7
Section 5 Exception Handling .............................................................................85
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Section 6 Interrupt Controller ............................................................................103
6.1
6.2
6.3
4.3.1
4.3.2
Pin Reset ............................................................................................................................. 83
Deep Software Standby Reset............................................................................................. 83
Watchdog Timer Reset ....................................................................................................... 83
Determination of Reset Generation Source......................................................................... 83
Exception Handling Types and Priority.............................................................................. 85
Exception Sources and Exception Handling Vector Table ................................................. 86
Reset ................................................................................................................................... 88
5.3.1
5.3.2
5.3.3
Traces.................................................................................................................................. 92
Address Error...................................................................................................................... 93
5.5.1
5.5.2
Interrupts............................................................................................................................. 95
5.6.1
5.6.2
Instruction Exception Handling .......................................................................................... 97
5.7.1
5.7.2
5.7.3
Stack Status after Exception Handling.............................................................................. 100
Usage Note........................................................................................................................ 101
Features............................................................................................................................. 103
Input/Output Pins.............................................................................................................. 105
Register Descriptions........................................................................................................ 105
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
Interrupt Priority Registers A to I, K, L, P to R
(IPRA to IPRI, IPRK, IPRL, IPRP to IPRR) .................................................... 109
Reset Status Register (RSTSR)........................................................................... 81
Reset Control/Status Register (RSTCSR)........................................................... 82
Reset Exception Handling................................................................................... 89
Interrupts after Reset........................................................................................... 89
On-Chip Peripheral Functions after Reset Release ............................................. 90
Address Error Source.......................................................................................... 93
Address Error Exception Handling ..................................................................... 94
Interrupt Sources................................................................................................. 95
Interrupt Exception Handling ............................................................................. 96
Trap Instruction................................................................................................... 97
Sleep Instruction ................................................................................................. 98
Illegal Instruction................................................................................................ 99
Interrupt Control Register (INTCR) ................................................................. 106
CPU Priority Control Register (CPUPCR) ....................................................... 107
IRQ Enable Register (IER) ............................................................................... 111
IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................. 113
IRQ Status Register (ISR)................................................................................. 118
Software Standby Release IRQ Enable Register (SSIER) ................................ 119
Rev. 2.00 Sep. 16, 2009 Page xi of xxviii