R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 687

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 16.16 Example of Operation for Transmission in Clocked Synchronous Mode
Synchronization
clock
Serial data
TDRE
TEND
TXI interrupt
request generated
Write transmit data to TDR and
clear TDRE flag in SSR to 0
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
All data transmitted
Start transmission
Figure 16.17 Sample Serial Transmission Flowchart
Initialization
TDRE = 1
TEND = 1
<End>
Yes
Yes
Yes
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
processing routine
Bit 0
Transfer direction
Bit 1
1 frame
No
No
No
[3]
[2]
[1]
Bit 7
TXI interrupt
request generated
[1] SCI initialization:
[2] SCI state check and transmit data
[3] Serial transmission continuation
Section 16 Serial Communication Interface (SCI)
Bit 0
The TxD pin is automatically
designated as the transmit data output
pin.
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0. However, the TDRE
flag is checked and cleared
automatically when the DTC or DMAC
is initiated by a transmit data empty
interrupt (TXI) request and writes data
to TDR.
Rev. 2.00 Sep. 16, 2009 Page 657 of 1036
Bit 1
TEI interrupt request
generated
Bit 6
Bit 7
REJ09B0414-0200