R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 416

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 I/O Ports
11.1.2
DR is an 8-bit readable/writable register that stores the output data of the pins to be used as the
general output port.
The initial value of DR is H'00.
11.1.3
PORT is an 8-bit read-only register that reflects the port pin status. A write to PORT is invalid.
When PORT is read, the DR bits that correspond to the respective DDR bits set to 1 are read and
the status of each pin whose corresponding DDR bit is cleared to 0 is also read regardless of the
ICR value.
The initial value of PORT is undefined and is determined based on the port pin status.
Rev. 2.00 Sep. 16, 2009 Page 386 of 1036
REJ09B0414-0200
Bit
Bit Name
Initial Value
R/W
Note: The lower six bits are valid and the upper two bits are reserved for port 6 registers.
Bit
Bit Name
Initial Value
R/W
Note: The lower six bits are valid and the upper two bits are reserved for port 6 registers.
The lower five bits are valid and the upper three bits are reserved for port F registers.
The lower five bits are valid and the upper three bits are reserved for port F registers.
Data Register (PnDR) (n = 1 to 3, 6, A, D to F, H, and I)
Port Register (PORTn) (n = 1 to 6, A, D to F, H, and I)
Undefined
Pn7DR
R/W
Pn7
R
7
0
7
Undefined
Pn6DR
R/W
Pn6
R
6
0
6
Undefined
Pn5DR
R/W
Pn5
R
5
0
5
Undefined
Pn4DR
R/W
Pn4
R
4
0
4
Undefined
Pn3DR
R/W
Pn3
R
3
0
3
Undefined
Pn2DR
R/W
Pn2
R
2
0
2
Undefined
Pn1DR
R/W
Pn1
R
1
0
1
Undefined
Pn0DR
R/W
Pn0
R
0
0
0