R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 784

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 ∆Σ A/D Converter
19.4.2
The ∆Σ A/D converter has six analog input channels. Single-ended input signal pins ANDS0,
ANDS1, ANDS2, and ANDS3 are used for channels 0 to 3. Channels 4 and 5 are capable of
converting differential input signals. Pin pairs ANDS4P and ANDS4N, and ANDS5P and
ANDS5N, are used for channels 4 and 5, respectively.
Channels for A/D conversion are selected by setting the corresponding CHn bit in DSADCSR to
1. A/D conversion is not performed on channels for which the CHn bit is clear. If all of the CHn
bits have been cleared to 0, no A/D conversion will be performed.
Setting two or more CHn bits to 1 places the ∆Σ A/D converter in multi-channel mode, where A/D
conversion of the signals on the selected channels proceeds in sequence (from channel 0 to
channel 5).
Values for canceling offsets of the single-ended input signals on channels 0 to 3 can be input as
register settings. These values are set in ∆Σ A/D offset cancel DAC inputs 0 to 3 (DSADOF0 to
DSADOF3). During A/D conversion on channel n, the value set in the DSADOFn register is
looked up and input to a 10-bit D/A converter that converts it to an analog signal, which provides
the level for canceling the offset on the analog input channel.
Table 19.4 shows the correspondence of the analog input channel settings.
Table 19.4 Correspondence between Settings and Analog Input Channels
Rev. 2.00 Sep. 16, 2009 Page 754 of 1036
REJ09B0414-0200
No.
0
1
2
3
4
5
Analog Input
Channel
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Selecting Analog Input Channels
A/D
Conversion
Channel
Select Bit
CH0
CH1
CH2
CH3
CH4
CH5
Analog Input
Pin
ANDS0
ANDS1
ANDS2
ANDS3
ANDS4P
ANDS5P
Single-Ended/
Differential
Input
Single-ended
Single-ended
Single-ended
Single-ended
Differential
Differential
Offset
Cancellation
DSADOF0
register
DSADOF1
register
DSADOF2
register
DSADOF3
register
ANDS4N pin
ANDS5N pin
Order of
Execution