R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 931
R5F61662N50FPV
Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R0K561622S000BE.pdf
(1070 pages)
Specifications of R5F61662N50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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24.2.10 Deep Standby Backup Register (DPSBKRn)
DPSBKRn (n = 15 to 0) is a 16-bit readable/writable register to store data during deep software
standby mode.
Although data in on-chip RAM is not retained in deep software standby mode, data in this register
is retained.
DPSBKRn is initialized by input of the reset signal on the RES pin, but is not initialized by the
internal reset signal upon exit from deep software standby mode.
24.3
When bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 in SCKCR are set, the clock
frequency is changed at the end of the bus cycle. The CPU and bus masters operate on the
operating clock specified by bits ICK2 to ICK0. The peripheral modules operate on the operating
clock specified by bits PCK2 to PCK0. The external bus operates on the operating clock specified
by bits BCK2 to BCK0.
Even if the frequencies specified by bits PCK2 to PCK0 and BCK2 to BCK0 are higher than the
frequency specified by bits ICK2 to ICK0, the specified values are not reflected in the peripheral
module and external bus clocks. The peripheral module and external bus clocks are restricted to
the operating clock specified by bits ICK2 to ICK0.
24.4
Module stop functionality can be set for individual on-chip peripheral modules.
When the corresponding MSTP bit in MSTPCRA, MSTPCRB, or MSTPCRC is set to 1, module
operation stops at the end of the bus cycle and a transition is made to a module stop state. The
CPU continues operating independently.
When the corresponding MSTP bit is cleared to 0, a module stop state is cleared and the module
starts operating at the end of the bus cycle. In a module stop state, the internal states of modules
other than the SCI are retained.
After the reset state is cleared, all modules other than the DMAC, DTC, and on-chip RAM are
placed in a module stop state.
The registers of the module for which the module stop state is selected cannot be read from or
written to.
Multi-Clock Function
Module Stop State
Rev. 2.00 Sep. 16, 2009 Page 901 of 1036
Section 24 Power-Down Modes
REJ09B0414-0200
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