R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 752

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 18 A/D Converter
[Legend]
X:
Note:
Rev. 2.00 Sep. 16, 2009 Page 722 of 1036
REJ09B0414-0200
Bit
3
2
1
Don't care
*
Bit Name
CKS1
CKS0
ADSTCLR 0
To set A/D conversion to start by the ADTRG0 pin, the DDR bit and ICR bit for the
corresponding pin should be set to 0 and 1, respectively. For details, see section 11, I/O
Ports.
Initial
Value
0
0
R/W
R/W
R/W
R/W
Description
Clock Select 1 and 0
These bits set the A/D conversion time.
Set the A/D conversion time while the ADST bit in
ADCSR is 0, and then set the conversion mode.
00: Conversion time = 46 states (max), ADCLK = Pφ
01: Conversion time = 87 states (max), ADCLK = Pφ/2
10: Conversion time = 168 states (max), ADCLK = Pφ/4
11: Conversion time = 332 states (max), ADCLK = Pφ/8
A/D Start Clear
This bit sets automatic clearing of the ADST bit in scan
mode.
0: Prohibits automatic clearing of the ADST bit in scan
1: Performs automatic clearing in scan mode if all the
mode.
selected channels complete A/D conversion.

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